The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs, and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, controlling the formation of conductive features becomes increasingly difficult as size decreases. Conductive layers are frequently formed using metallization processes such as damascene and dual damascene processes. Damascene processes utilize one or more masks to etch openings in an insulating layer of an IC wafer. Typically, photolithography is used to transfer the mask patterns to the wafer. Each photolithographic mask in the set has a pattern formed by transmissive or reflective regions. During exposure, radiation such as ultraviolet light passes through or reflects off the mask before striking a photoresist coating on the wafer. The pattern is thus transferred onto the photoresist, which is then selectively removed to reveal the pattern. The wafer then undergoes processing steps that take advantage of the shape of the remaining photoresist to create cavities in the insulating layer. The openings are filled with a conductive material, such as copper, to form wires, vias, interconnects, and other shapes. With each subsequent improvement in geometry size, additional challenges in metallization arise. Although existing metallization procedures have been generally adequate, they have not proved entirely satisfactory in all respects.